An Energy Efficient and Temperature Stable Digital FLL-Based Wakeup Timer With Time-Domain Temperature Compensation

This brief presents an on-chip digital intensive frequency-locked loop (DFLL)-based wakeup timer with a time-domain temperature compensation featuring a embedded temperature sensor. The proposed compensation exploits the deterministic temperature characteristics of two complementary resistors to stabilize the timer’s operating frequency across the temperature by modulating the activation time window of the two resistors. As a result, it achieves a fine trimming step (± 1 ppm), allowing a small frequency error after trimming (<± 20 ppm). By reusing the DFLL structure, instead of employing a dedicated sensor, the temperature sensing operates in the background with negligible power (2%) and hardware overhead (< 1%). The chip is fabricated in 40 nm CMOS, resulting in 0.9 pJ/cycle energy efficiency while achieving 8 ppm/°C from −40°C to 80°C.0F