An Event-Driven Cardiac Monitoring System Based on a Low-Power Atrial-Fibrillation Detection ASIC With a Sensitivity of 92.5%

This letter presents an event-driven cardiac monitoring system for atrial-fibrillation (AF) detection through the co-design of a low-power application-specific integrated circuit (ASIC) and a back-end processor. Only when the AF abnormality is detected, the ASIC wakes up the processor from the standby mode, which transfers the AF episode from a front-end static random-access memory (SRAM) to the PC through a universal asynchronous receiver-transmitter (UART) interface. Afterward, the processor reenters the standby mode to reduce power consumption. An improved Pan and Tompkins algorithm is proposed, which achieves 49.7% power reduction compared with the conventional design. The R-peak detection and Kolmogorov–Smirnov-test (KS-test)-based AF-diagnosis algorithms are implemented as an ASIC in a 0.18-
μ
m CMOS technology and achieve an AF-detection sensitivity of 92.45%. The system shows promise for realizing the next-generation implantable cardiac monitoring systems.