Chiplets and Next-gen Packaging Technologies in University Education

Gordon Moore famously predicted in his ”Moore’s Law” paper that it might become more cost-effective to construct extensive systems using smaller, individually packaged functions interconnected together. More than half a century later, the structure of the System-on-a-Chip (SoC) changes significantly with the partitioning of a monolithic die into smaller chiplets: packaging becomes one of the main focuses when designing a chip and the way the initial functionality is partitioned between multiple chiplets and how these are interconnected means we have to shift our perspective to Systems in Package (SiP). Standards for interconnecting chiplets play a huge part in making chiplet technology the next evolutionary step in electronics. For this to be widely adopted across the industry there needs to exist specifications about electrical signaling, types of packaging, channels length, spacing, and routing between chiplets so that the chips of the future can have diverse functionality and use IP from different companies. Such standards have already emerged in the past two years and we will cover some of the proposed ideas. In the present paper, we propose solutions at the university curricula level to introduce the subjects mentioned above, as well as open-source tools which will enable students to practice theoretical notions about chiplets by designing and simulating virtual SiPs.