ENEST - Efficient Interrupt Nesting for RISC-V based CPUs

Embedded systems are typically driven by external and internal events, implemented by means of (static priority) interrupts. Response time can be improved by allowing for interrupt nesting, i.e., allowing for a higher priority interrupt to preempt the execution of a currently running interrupt handler. In this paper we study interrupt nesting for the RISC-V architecture and propose ENEST: a stacking approach with predictable overhead, minimizing both blocking and interference. Claims of the proposed mechanism are validated on the modern ESP32-C3 single core MCU. Our experimental results quantify blocking and interference, allowing further static scheduling analysis of ENEST based applications.