Implementation Strategies for Highly-accurate and Efficient Frame Synchronization Modules in Satellite Communication Receivers

Satellite communication standards commonly define a frame structure for the physical layer composed of a preamble, segments of modulation symbols, and segments of pilot symbols to aid synchronization algorithms. Detecting the start of received frames is therefore an essential operation, and its accuracy can be compromised by the presence of a large Doppler shift and the quantization introduced when implementing the algorithm on digital systems. In this work, we investigate the trade-off between accuracy and resource consumption for hardware implementations of frame synchronization modules able to support the satellite communication protocol defined by the standard CCSDS 131.2-B-1, and we define the hardware architecture corresponding to the best solution. In order to support high data-rate links, we illustrate also the methodology to derive a parallel implementation that allows increasing throughput without replicating all the hardware resources. We also verified such architectures by means of RTL simulations of a corresponding bit-true model written in VHDL. The presented work can be used by hardware designers as a guideline to implement highly-efficient frame synchronization modules in hardware and for any space communication protocol based on a frame format similar to the one of the CCSDS 131.2-B-1. To the best of our knowledge, this is the first work in literature that proposes parallel architectures for frame synchronization in space applications.