Comparative Analysis of Reversible Logic Gates and Reversible Decimal to Binary Encoders using Verilog

Reversible computing in CMOS design and Quantum computing helps to optimize the power consumption in circuits. This paper presents the comparative analysis of four reversible Decimal to Binary Encoders (D2BE) and analyses ten different reversible logic gates. Different parameters are analyzed including area, delay, power, garbage bits etc. Feynman gate is the most efficient as it has 5.259ns default delay, 6.513ns I/O port max delay and consumes one slice LUT followed by Toffoli and BJN gate. D2BE-1 and D2BE-4 consumes least dynamic power i.e. 1mW at V(low) and 2mW at V(high), where D2BE-1 is made using 10 reversible gates and D2BE-4 is made using 16 reversible gates. The reversible logic gates and reversible D2BE are synthesized and implemented using XILINX 14.7 ISE and focuses on SPARTAN 6 FPGA family device.