FPGA-Based Efficient MLP Neural Network for Digit Recognition

Field Programmable Gate Array (FPGA) based accelerators for Convolutional Neural Networks (CNN) have been developed to address the need for high performance and reconfigurability. The computation throughput of these accelerators may not match the memory bandwidth provided by the FPGA platform, which limits performance. Therefore, a structural improvement in the developed Multiply and Accumulate (MAC) unit within the CNN layers can substantially improve the performance of the network. This work proposes a Multi-Layer Perceptron (MLP) model, developed in Verilog HDL, and synthesized on Xilinx Kria (xck26) FPGA. The model uses the MNIST dataset used for digit recognition as input, implemented using Python on Spyder IDE. The accuracy of the model is obtained for different numbers of epochs and a maximum accuracy model is developed. The weight files from this maximum accuracy model and the bias files are extracted. These weight and bias files are provided as inputs to the MLP model developed in Xilinx Vivado. The model is verified by providing a known input to the Python model and extracting these weights to verify the model in Verilog HDL. The CNN model gives an accuracy of 99.68% for the training dataset and 94.5% for the testing dataset. The utilization of the FPGA resources for the proposed MLP design is 41.32% more efficient than a conventional MAC implementation.