Research on countermeasures against FPGA memory bit upset in the merging unit device

FPGA chip memory bit upset may cause disturbance of the sampling data output by the merging unit device, which increases the risk of protection mis-operation or rejection, and endangers the safety of the power system. In the FPGA program design of the self-reliance merging unit device, the data redundancy verification measure is added to realize real-time detection and blocking of memory bit upset. The effectiveness of countermeasures is verified by injecting fault bits upset at key points in the data chain. The neutron irradiation acceleration test conducted at the China Spallation Neutron Source further proves that the proposed method combined with the ECC error correction function can significantly enhance the error prevention ability of the merging unit device and reduce the risk of substation protection failure.