Comprehensive Investigation on CM Voltage, Bearing Current, and THD in MLI-fed Motor Drives using SPWM

In recent years, multilevel converters have received significant consideration as power-conversion systems for demanding applications requiring high power and power quality. Furthermore, Pulse-width sequences have been recognized as the primary defining factor of common-mode voltage (CMV), which through parasitic capacitances, generate bearing current and shaft voltage, which are major points of failure for electric drives. This research focuses on carrier-based sinusoidal pulse width modulation strategies for three five-level inverters, including cascade H-bridge (CHB), neutral-point-clamp (NPC), and packed U-cell (PUC). Multilevel inverter-fed motor drive and the equivalent circuit of parasitic capacitances in the inverter-driven motor are modeled and simulated using MATLAB/SIMULINK, and the results are compared and discussed.