Energy-Efficient CNTFET-RRAM Based Ternary Logic Design

The ever-increasing demand for portable electronic items has led to new innovations in ultra-low power VLSI design. The Multivalued Logic (MVL) is a very potential alternative to the energy consumption due to interconnect issue in binary logic design. This paper proposes new ternary circuits using Carbon-nanotube-field-effect transistors (CNTFET) and resistive random-access memory (RRAM). This paper aims at optimizing their energy efficiency by mitigating the power delay product (PDP). The proposed circuits include the standard ternary inverter (STI) and 1-bit ternary half adder (THA). The proposed circuits are simulated at a VDD of 0.9V and their energy efficiency is compared with some recent designs in the literature. The simulations are carried in Synopsis HSPICE tool using standard 32nm CNTFET and Stanford/ASU RRAM model files. The power consumption and PDP of the proposed STI is 42.62% and 56.57% less than the least power consumption and PDP of other designs under considerations. The power consumption and PDP of the proposed THA is 32.88% and 66.44% less than the least of these two metrics of other designs under consideration.