Designing the Complete Working for the Resolution of 10 Bit SAR ADC with its Improved Parameters Used in Various Application for Digital Circuits in SCL Technology

This report suggests the resolution of the 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) focused on binary search algorithm for approximate on data, optimized used for 1MSPS sampling speed. SAR ADC's major construction blocks include high-speed latched comparators, R-2-R based Digital to Analog Converter (DAC) & a Digital Control Logic which transfers & saves comparator information. A system is designed to use the software suite of Cadence Virtuoso in SCL 0.18 micrometer
$(\boldsymbol{\mu} \mathbf{m})$
CMOS method. The voltage of distribution used in this function is 3.3 V. The maximum voltage spectrum is 0.65-2.65 V and the equivalent frequency of 1 LSB is 1.9 mV. It also has a 55.45 dB signal-to-noise ratio (SNR) and an 8.7- bit effective-number-of-bits ratio (ENOB).