A Comparative Analysis of High-k Gate Dielectrics on 30nm Fully Depleted Silicon on Insulator (FD SOI) MOSFET and NMOS Devices

This work focuses on various high-k dielectric materials as gate oxides to compare the performance characteristics of 30nm Fully Depleted Silicon on Insulator (FD SOI) MOSFET and NMOS devices. To examine the effects of various device design settings, electrical characteristics such as subthreshold swing, drain current, leakage current, threshold voltage, and current ratio are studied. The results show that FD SOI MOSFETs have benefits over traditional NMOS. Notably, FD SOI MOS-FET threshold voltage (94.66%) and leakage current decreased significantly as source/drain doping was reduced. Additionally, materials with greater dielectric constants showed less leakage current, improving performance measures. The research shows that FD SOI MOSFET with hafnium oxide as the gate dielectric witnessed considerable improvements in current ratio (246.61%) and sub-threshold swing (92.41%) using 2-Dimensional simulation software. Insights into device design optimization for improved semiconductor performance are provided in this work, with implications for cutting-edge circuit design.