Implementation of Low Power VLSI Architecture using Adiabatic Logic

The need of low power consuming CMOS designs has increased to meet the emerging technology raise in the market. In CMOS, power that is lost as heat energy during the discharging phase can be eliminated by using ‘Adiabatic Logic’. This paper brings you the implementation of 2:1 Multiplexer (MUX) and 1:2 De-Multiplexer (DE-MUX) using Adiabatic Logic. Our simulation results reveals that the power consumption of MUX and DE-MUX is reduced by 60% and delay is reduced by 80% according to the 90, 180 nm technologies. This Low Power Consuming MUX and DE-MUX can be used in the fields of parallel data communication, design of computer memory, data transmission.