An UVM-Based Verification Platform for Hardware and Software Co-Design

As chips grow in size and complexity, functional verification in a software environment is increasingly unable to meet the needs of efficient chip production processes. Therefore, the improvement of verification efficiency becomes critical. For the bus subsystem including AXI, AHB, AXI2AHB-bridge and AHB2APB-bridge, a coverage-driven Universal Verification Methodology (UVM) hardware and software co-simulation verification platform is built by taking advantage of the high-speed performance and object oriented programming of the Field Programmable Gate Array (FPGA) hardware platform, which effectively improves the verification efficiency of Intellectual Property (IP) cores based on AXI, AHB and APB protocols and reduces the development cycle.