A 2nd-Order Noise-Shaping SAR ADC with Reused Dynamic Amplifier Assisted Integrator

In this paper, a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with standard 2nd-order Noise-Shaping (NS) function is proposed. The design employs a ping-pong structure and a reused closed-loop dynamic amplifier to realize the 2nd-order noise shaping, which effectively reduces the non-ideal factors such as in-band quantization noise, comparator noise and others. This can significantly improve ADC accuracy and improve power efficiency. The SAR ADC proposed in this paper utilizes V
CM
-based switching scheme and bottom sampling to reduce the impact of charge injection while reducing dynamic power consumption. The proposed architecture is designed in 180 nm CMOS technology, which realizes a peak Signal-to-Noise and Distortion Ratio (SNDR) of 69.3 dB at sampling frequency of 32 MS/s, and Schreier Figure of Merit (FoM) reaching 159.8 dB.