An Energy-Efficient and Area-Saving Capacitor Switching Scheme for SAR ADCs

This paper presents a switching strategy to diminish energy consumption and minimize the capacitance area overhead in Successive Approximation Register Analog-to-Digital Converter (SAR ADC). The Power Area Dual Saving (PADS) switching scheme combines bottom plate sampling technology and a novel switching method, saving the highest and second highest capacitors in CDAC and eliminating the power consumption of the first two conversion cycles. At the same time, this switch scheme only switches for a single capacitor each time (except for the first conversion), greatly reducing the complexity of the switch-switching logic. Compared with traditional switching schemes, this scheme reduces the area of capacitor by 75% and the switching power consumption by 97.7%. To verify the feasibility of this switching strategy, a high-precision 14-bit SAR ADC was used for validation in this paper. The results indicate that this strategy can effectively demonstrate its advantages in energy efficiency and chip area overhead.