A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces

This brief presents a single-ended receiver (RX) with data edge (DE) sampling to reduce the clock frequency and phase for memory interfaces. The proposed technique samples data at the data edge per 2-unit intervals (UIs). When the data transition occurs, the comparator generates the decision error because the cross point does not have a vertical margin. To have a sufficient vertical margin, the proposed RX uses a high-pass filter (HPF) for the correct decision. In contrast, when there is no data transition, the comparator generates the correct decision without the HPF because the vertical margin of the data is already large. For the proposed DE sampling, the RX requires an HPF and two comparators that receive the input and output of the HPF. The inputs of the two comparators with different vertical margins generate the decision time differences between the two comparators. A time-based transition detector (TBTD) uses these decision time differences to determine whether a data transition has occurred. Subsequently, a decoder recovers the two consecutive data simultaneously using the outputs of the TBTD and two comparators. This brief is fabricated using a 28-nm CMOS technology, and the core area occupies 0.0015 mm 2. The RX core consumes 11.1 mW at 13-Gb/s and achieves an energy efficiency of 0.85 pJ/bit.