A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer

This article presents an area-efficient 10-bit source-driver IC (SD-IC) for mobile displays. Addressing the challenge of exponential die area growth associated with higher digital-to-analog converter (DAC) resolution dominating color depth, we propose a three-stage-cascading interpolation design solution. In the first stage, a two-output voltage selector selects adjacent voltages from the global resistor string. The proposed overlap-switch merging (OSM) technique reduces its size by two times compared to conventional two-output selectors. The second-stage interpolation employs a successive-approximation-register (SAR)-interpolating switched-capacitor (SI-SC) DAC, enhanced with bit-adaptive switch-size (BASS) modulation to minimize the switching errors. The proposed SI-SC DAC also features an intrinsic two-output design for further interpolation in the subsequent stage. In the last (third) stage, a super-class-AB operational transconductance amplifier (OTA)-based buffer amplifier performs accurate 1-bit true-dc interpolation with no overhead while driving the final output with a fast slew rate. The prototype chip was fabricated in a 180-nm 1.8/5-V CMOS process. The maximum differential nonlinearity (DNL) and integral nonlinearity (INL) were measured to be −0.37 and 1.17 LSB, respectively, in a 10-bit resolution. The maximum deviation of voltage outputs (DVOs) achieved was 15.5 mV. The proposed chip exhibits a source channel size of 2211
$\mu \text{m}^{2}$
, which is the smallest reported to date, along with a competitive slew rate of 44 V/
$\mu \text{s}$
measured at
$C_{\text {Load}}\,\,=$
100 pF.