Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs

In this work, the influence of process-induced sidewall inclination on direct tunneling gate leakage current (
${I}_{G}$
) in the trapezoidal (Tz) channel NW GAA MOSFETs has been comprehensively investigated using experimental data and the TCAD simulations results. Variability in device parameters as channel length, height, and width have been taken into account when we examined gate leakage current. The side-wall inclination angle has a significant influence on the gate leakage current, where a rise in
${I}_{G}$
of up to two times is observed when the inclination angle is increased from 0° to 20°. Moreover, it has also been observed that the direct tunneling gate leakage current is significantly influenced by the gate overlap and underlap areas.