Stability of GaN HEMT Device Under Static and Dynamic Gate Stress

In this work, we investigated the stability of a
${p}$
-GaN gate with high electron mobility transistors (HEMTs) including an internal integrated gate circuit. A circuit was designed to improve
${p}$
-GaN gate stability by using capacitance to release the hole into the
${p}$
-GaN layer to mitigate the threshold voltage shift. Through pulse I-V measurement and positive bias temperature instability (PBTI) test, the carrier transporting behavior in the gate region achieved dynamic equilibrium at 5 V gate bias. The positive gate shift
$(\Delta V_{\mathrm{ TH}})$
of 0.4 V is observed with increasing voltage from 3 V to 8 V;
$\Delta V_{\mathrm{ TH}}$
initially drops smoothly after release stresses by external capacitance discharge. Finally, integrated passive components and
${p}$
-GaN gate HEMT circuit are recommended to mitigate the
$V_{\mathrm{ TH}}$
instability for E-mode HEMT.