Investigation of Cylindrical Gate All Around Field Effect Transistors Exploring Variation in Low Voltage Using Visual TCAD

This paper conducts a comprehensive simulation study on the gate all around field effect transistor (GAAFET), specifically examining the impact of temperature variations at 300K and a doping concentration of 1 × 10
^-18
cm
^-3
. The device architecture has three fin structures, and gate material surrounds the channel. This configuration is strategically designed to mitigate the short-channel effect (SCE) and minimize electrostatic capacitance. The study meticulously assesses a range of critical parameters, including threshold voltage (V
th
), I
on
/I
off
ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The threshold voltage (V
th
), or gate voltage necessary to start the transistor's conduction, of the GAAFET device under research is 0.37 volts (V). This device mainly shows that SS, a critical parameter that measures how fast the drain current changes about the subthreshold region's gate voltage, impacts a big part, about 78%, of the device's performance. Furthermore, 28% of the device's behaviour is explained by DIBL, which is the term used to describe the phenomenon of reduced threshold voltage brought on by short-channel effects. Additionally, it has been discovered that the device's I
on
/I
off
current ratio is 2.35 × 10
^{^-7}
µA, which represents the contrast between the device's “on” and “off” states. The device compares the performance of SS and DIBL in FinFET. Therefore, GAAFET is a suitable device with less leakage current.