Approximate Compressor for Efficient Multiplication in Image Processing Applications

Approximate computing is a promising candidate for minimizing the energy consumption of various image processing Algorithms, which also have error tolerable characteristics. The image processing algorithm intensively consists of matrix multiplications where the approximate multiplier (positive compressor, Negative compressor) replaces the exact multipliers for energy reduction. This paper discusses the design and analysis of the two approximate multiplier by using the two approximate 4–2 compressors with reduced delay, area, power, and comparable accuracy with the existing multipliers. The NC based 8×8 multiplier (NM) consumes 30.17% and 3.85% less power than exact 8×8 and PC 8×8 multiplier(PM) respectively. Similarly the LUT utilization of NC based 8×8 multiplier is 5.4% lesser than exact 8×8 and 2.7% less than the PC based 8×8 multiplier. The proposed approximated multiplier is used in the Sobel edge detection algorithm by replacing complex normal multiplier operations. The core part of the edge detection algorithm with approximate multiplier is implemented using the Verilog HDL program and the MATLAB is used to give the input image to the Verilog code based approximate multiplier and then the edge detected output is again fed to MATLAB and finally the edge detected output is displayed using MATLAB too.