FPGA Implementation of Modified Compressor for Signal Processing Applications

Multiplication plays the key role in digital signal processing, digital image processing, mobile computing, very large-scale integration (VLSI), embedded systems and several other fields. To obtain better, accurate and fast output in today's technology world we need efficient processors. To accomplish this task, we have designed a novel multiplier using (7,3) and (15,4) compressor. The high compression ratio compressors are used in the multiplication process to add the partial products results in better performance. Further, proposed method performance parameters are compared with all existing literature and found that our design is better than the existing researches.