Design of a Hardware Accelerator Supporting Dual-Mode FIR Filtering Based on the Rocket-Chip Platform

This paper presents the design and implementation of a hardware accelerator that supports dual-mode FIR filtering, integrated within the Rocket-chip platform. To seek the optimum choice between area and speed, three distinct FIR filter designs are discussed in this paper. The Specially shared and reconfigurable hardware ensure high throughput and flexibility in the ECG pre-processing domain. The accelerator was implemented under the scala framework, and simulated on FPGA with a system clock of 100MHz. The 1800-point ECG data input was obtained from MIT-BIH database, the filter quality was assessed and analysed in Matlab.