A Hybrid Approach to Optimized n-bit Multiplier Design on FPGA Leveraging Recursive-Wallace Tree with AI Centric Enhancements for FIR Filters and Neural Network Inference

This paper unveils a technique to optimize nbit Multipliers by introducing a hybrid AI-based approach to decrease latency and increase efficiency, crucial for specialized applications like FIR filters and Neural Network Inference. It combines Wallace tree and Recursive algorithms, harnessing their combined merits to accelerate multiplication. Moreover, it employs a distinctive cache management strategy and addresses hash collisions utilizing past data. The cache preserves output values for corresponding inputs, mitigating the necessity for repeated multiplications of identical values at different time instances, thereby enhancing the implementation. This framework also integrates the Least Recently Used (LRU) strategy to efficiently manage cache entries, further augmenting the process efficiency. The decrease in latency is presented in this paper after implementing the multiplier in Intel's Quartus Prime. The proposed multiplier exhibits an impressive 49% reduction in delay compared to conventional multipliers, and still achieves a notable 16% decrease when compared to Recursive Multipliers; efficiency is further increased as there is a 13% increase in slack compared to Recursive and a substantial 59% increase when compared with conventional multipliers. ALTERA DE2-115 FPGA is used to simulate the hardware output of the multiplier.