Design and Analysis of a FinFET Based Multiplexers for Ultra Low Power Applications using GDI Technique

This study proposes the design and analysis of 2:1, 4:1 and 8:1 multiplexer (MUX) implemented using FinFET technology for low power applications. The proposed multiplexer architecture has been designed using Gate Diffusion Input (GDI) technique. The unique characteristics of FinFET and reduced short-channel effects in addition with GDI technique may leverages to achieve energy efficient multiplexer. This project investigated the 2:1, 4:1 and 8:1 multiplexer for power dissipation, delay, and power delay product (PDP). This work is carried out by using Cadence Virtuoso Tool with 18 nm FinFET technology. Furthermore, the results of proposed GDI based 2:1, 4:1 and 8:1 MUX have been compared with already existing pass transistor logic (PTL) based 2:1, 4:1 and 8:1 MUX in terms of delay, power, and PDP. This research will contribute towards the advanced transistor technologies for achieving ultra-low power consumption in digital circuits and energy-efficient electronic systems for next-generation computing applications.