8-Bit Dual Core SIMD Processor with Assembler

SIMD (Single Instruction, Multiple Data) processor is a specialized type of microprocessor architecture designed to accelerate parallel processing tasks by executing a single instruction on multiple data elements simultaneously. This work focuses onto the design and implementation of an 8-bit Single Instruction Multiple Data (SIMD) Computer architecture which incorporates a dual core with a single control unit, it executes various logical, arithmetic, relational, Load/Store, and branch operations. Further enhancement of parallel processing capabilities and improvement of overall performance by incorporating a 4-stage pipelining mechanism that is, Fetch, Decode, Execute, and Write Back stage, in which each stage occupies a single clock cycle. Improving the utilization of the processor by the implementation of Assembler and by using several compiler techniques for prevention of hazards occurring during pipelining such as instruction hazards and data hazards using Intel Quartus Prime tool.