Design Considerations, Development, and Experimental Validation of a 3.3 kV SiC-Based Reverse Voltage Blocking Half Bridge Module for Current Source Inverter Application

Wide-band gap (WBG) devices have enabled the re-emergence of current source inverters (CSIs). With increased
$dv/dt$
and
$di/dt$
of WBG devices, the parasitic inductances in the power loop and gate loop are critical in reducing the induced voltage at the devices. This paper presents the design consideration and development of a low inductance 3.3 kV silicon carbide (SiC) based reverse voltage blocking (RVB) half-bridge (HB) module for CSI-based applications. The module comprises a SiC-MOSFET (3.3 kV/50 A die) and a SiC-MPS diode (3.3 kV/50 A die) to form a 3.3 kV SiC-based RVB switch in the HB configuration. The module inductance is estimated using ANSYS Q3D. The impact of the unequal busbar parasitic inductances between the CSI phases on the RVB switch in the HB module is discussed considering the medium voltage (MV)
$dv/dt$
and
$di/dt$
limits. The increased substrate thickness helps reduce the module's parasitic capacitance and thus reduces electromagnetic interference (EMI) concerns. The static and dynamic characterization of the RVB switch or current switch (CS) is performed to demonstrate the functionality of the proposed module. The static and dynamic characterization is used to understand a three-phase CSI system's switching frequency limits, heat sink, and cooling requirements. The steady-state hardware result and the dynamic response of the three-phase CSI with the proposed module are presented.