Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation

We present a dynamic random access memory (DRAM) design technology co-optimization (DTCO) methodology that allows the optimization of the DRAM cell structure in the presence of contact resistance variation, trap-assisted tunneling (TAT) leakage variation, and storage node capacitance variation. We showcase our methodology features and results by studying the optimization of a DRAM metal gate work function under the constraints of writeability, retention time (tRET) performance, and robustness to the row hammer effect. Our simulation results show that DRAM performance and its reliability are strongly affected by the contact resistance variations induced by random discrete dopants (RDDs) and can be maximized by means of DTCO-based engineering of contact area and doping concentrations. Our findings also highlight that focusing the optimization on leakage reduction can pay higher dividends than increasing storage node capacitance or improving writeability.