A structured graphical tool for analyzing boundary scan violations

The boundary scan test methodology is becoming an increasingly important approach for testing chips, modules and boards. Commercial boundary scan verification tools are now available which provide a system of checks not only for IEEE 1149.1 but other methodologies such as IBM Boundary Scan. A key factor in the effectiveness of boundary scan verification systems is found in the accuracy and flexibility of companion analysis tools used to correlate the violated boundary scan rule with the subject logic structure causing the violation. This paper presents the design and deployment of a graphical system for pinpointing sources of boundary scan rules violations. The paper begins with a cursory review of boundary scan methodologies including IEEE 1149.1 and IBM Boundary Scan. This is followed by a brief presentation of the boundary scan verification process used in IBM's TestBench tool. The body of the paper is focused on boundary scan verification rules and the associated message analysis. The paper concludes with future plans under consideration to improve both the reach and usability of graphical message analysis for boundary scan verification.