A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme

Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta–sigma modulators (CT
$\Delta \Sigma $
Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [−100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (
$\leq $
10 MHz), their performance is limited by the 1/
${f}$
noise generated by the near-minimum size devices used in their wide-bandwidth input stages. This, in turn, limits their use in radio receivers intended to cover both the AM and FM bands. In this work, a multi-path multi-frequency chopping scheme is proposed to suppress 1/
${f}$
noise, while preserving interferer robustness, thermal noise levels, and linearity. Implemented in a CT
$\Delta \Sigma $
analog-to-digital converter (ADC) sampling at 6 GHz, it achieves a 22
$\times $
reduction in 1/
${f}$
noise, as well as 122-dBFS SFDR and −98.3-dBc THD in a 120-MHz BW.