A 0.392ms FPGA-Based Channel Estimation Design Implementing Fine Symbol Timing Offset and Residual Carrier Frequency Offset Cancellation for 2×4 MIMO Uplink in 5G Microcells

An FPGA-based channel estimation design is presented to combine the fine symbol time offset (FSTO) and the residual carrier frequency offset (RCFO) algorithms. The proposed architecture is highly scalable, supporting multiple antenna configurations and varying pilot symbol lengths. In this paper, a full design flow from algorithm analysis to implementation and optimization is described with an FPGA demonstration. The
$\mathbf{2}\times \mathbf{4}$
MIMO Uplink system has been implemented in Xilinx UltraScale VCU118 to achieve a low latency computation time of 0.392ms., less than the 0.5ms 5G transmission time interval (TT1), leaving room for other computations and system up-scaling.