3D Van der Pauw Device for MOS Channel Characterization on 4H-SiC Trench Sidewalls

In this letter, the van der Pauw test structure integrated on the trench sidewall (3D-VDP) is designed and demonstrated, to achieve an explicit characterization of 4H-SiC UMOS channel properties. 3D-VDP removes two types of critical problems in UMOS channel characterization: parasitic resistance and dimension error. Such a microscopic structure was implemented by repetitive epitaxial growth and implantation. By comparing properties between a UMOS channel on the trench sidewall and a planar MOS channel fabricated on epi-surface, it was confirmed that they are consistent under our experimental conditions. In the experiment, because we employed a 4° off-axis substrate, impacts of the channel plane orientation were systematically obtained by changing the trench direction. According to the relationship between the channel plane orientation and the MOS channel resistivity, it is important to refrain from trench tilting toward Si-polar orientation even by several degrees. Furthermore, Hall effect analysis revealed that trench tilt toward Si-polar orientation results in both decreasing in the carrier density and mobility in the MOS channel.