A Novel Search-Based Compute-in-Memory Minimum Values Generation Scheme for Low-Complexity LDPC Min-Sum Decoding

The generation of the minimum values (the first two minima and the index of the minimum) of numerous variable-to-check messages (V2CM) is the major bottleneck in efficient min-sum decoding of low-density parity-check (LDPC) codes. This brief proposed a novel search-based compute-in-memory (CIM) based minimum values generation (MVG) scheme with two search strategies sharing two core circuits, which avoids the hardware-costly cascading of comparators and multiplexers necessary in conventional comparison-based schemes. The two shared core circuits include (1) the multi-bit content-addressable memory (MCAM) circuit for fast and concurrent search on stored operands (V2CMs) and (2) the search result evaluation (SRE) circuit to generate search result evaluation signals for the update of the minimum values. The two search strategies include (1) the sequential traversal search (STS) strategy and (2) the self-adaptive dichotomic search (SaDS) strategy for low- and high-precision decoding scenarios. Eventually, with the 14nm FinFET design kit, simulation results show that, in terms of area-delay complexity (ADC), the proposed MVG scheme achieves an average of 83% reduction in both low- and high-precision-scenarios, over the conventional comparison-based schemes.