A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering

A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback architecture is presented in this article. The proposed architecture not only overcomes the noise shaping frequency limitation seen in a conventional dual-feedback PLL, but also solves stability and noise overhead issues that were present in the prior art. Due to the wide loop bandwidth that can be achieved because of the effective quantization noise suppression by the proposed method, the fractional-N synthesizer is realized with low phase noise and jitter using only ring voltage-controlled oscillator (VCO), allowing an implementation that is low area and robust to magnetic coupling compared with ones using $LC$ -VCOs. A proof of concept prototype is implemented in 65-nm CMOS technology that achieves a −229.4-dB jitter-power figure-of-merit (FoM) and −49-dBc worst-case fractional spurs with a 40-MHz reference.