CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)

We propose a Non-Volatile Ternary Content Addressable Memory (nvTCAM) by utilizing two Resistive Random-Access Memory (RRAM) cells integrated with individual selector transistors (i.e., 2-Transistor, 2-RRAM). A 2T2R cell configured either in complementary resistive switching mode (i.e., if one 1T1R cell is in low resistance state then the other cell will be in high resistance state or vice-versa) or both RRAMs in high resistance state is utilized to implement a single nvTCAM unit. Through Monte-Carlo (MC) simulations and power supply scaling (i.e.,
$V_{DD}$
varying from 1.4 V to 2.2 V) effects, reliability of the proposed cell was studied. Moreover, we performed the simulations for various sizes of word length from 1-bit to 64-bits and calculated the energy and delay parameters. We compared the proposed nvTCAM cell with various existing CMOS/NVM (Non-Volatile Memory) designs. Our proposed nvTCAM design provides
$\geq 2\times$
area efficiency as compared to CMOS-NVM counterparts and even upto
$\sim 6\times$
area saving with respect to CMOS-based volatile TCAM. The proposed design achieves atleast 1.68× to 2.27× energy efficiency, as compared to existing CMOS/RRAM implementations. Moreover the energy saving is further increased upto
$\sim 1400\times$
as compared to magnetic/ferroelectric-based nvTCAM counterparts.