OD-REM: On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet Inspection

regex (regular expression) matching is one of the most demanding stages of deep packet inspection process. Numerous studies explored FPGA-based acceleration techniques for regex matching. Existing FPGA-based regex matching engines, such as Grapefruit, assume that each packet potentially match all rules and employ a pipelined structure where each packet traverses each automata sequentially. However, in practical DPI systems, it is often the case that only a small subset of rules needs to be applied to a given packet. Consequently, subjecting every packet to processing by all automata incurs significant throughput wastage. In fact, prior to regex matching, a fast pattern matching stage can ascertain the rules that a packet may satisfy (these rules are referred to as ‘candidate rules’ for the packet). Based on this observation, we propose OD-REM, an On-Demand Regex Matching architecture on FPGAs. Within OD-REM, each packet is processed by automata corresponding to its candidate rules only, with these automata being dynamically generated as needed. We design a simple yet efficient scheduler to allocate packets to their candidate automata. We implemented ODREM containing 64 automata on Xilinx U200 smart NIC. ODREM obtained a throughput of 27. 6Gbps (13.8times faster than Grapefruit), and consumed 6.06% logic resources and 10.28% BRAMs of the on-board FPGA (Xilinx VU9P), respectively. It is worth pointing out that OD-REM only need more UltraRAMs to accommodate more regex rules, leaving logic resource and BRAM consumption unchanged.