An Efficient Dataflow for Convolutional Generative Models

Convolutional generative models have achieved significant success in the field of artificial intelligence in recent years. These models typically rely on numerous convolution and transposed convolution operators, both of which are highly computationally intensive but present distinct computation patterns. As a result, accelerating the convolutional generative models can be challenging, particularly when the transposed convolution is likely to become performance bottleneck. In this paper, we propose a dataflow for overcoming the challenge and effectively accelerating both computation-hungry operators of convolutional generative models in the unified architecture. Additionally, we have devised specific tiling schemes to flexibly map both convolution and transposed convolution and fully reuse hardware resources. To demonstrate the effectiveness of our approach, we implemented DCGAN and ST on the Xilinx ZCU102 platform. Our experiments show that the proposed dataflow can reduce memory cost by up to 36%, achieving comparable performance for both convolution and transposed convolution.