DELTA-V: An Open-Source High-Level Synthesis Driven ASIP Design Automation Tool for RISC-V Microprocessors

Application-Specific Instruction-set Processors are crucial for optimizing performance and energy efficiency in specific applications while retaining compiler-supported programmability, especially in open-standard architectures like RISC-V. To meet the increasing demand for ASIPs, rapid design and prototyping are essential. High-Level Synthesis automates the translation of high-level software descriptions into hardware, significantly reducing design time. However, it’s important to note that while HLS provides designs, it doesn’t directly create RISC-V cores. ASIP designers bridge this gap, but must also be proficient in hardware description languages like VHDL. In this work, we introduce DELTA-V, a project that seamlessly combines OpenASIP and AMD Vitis HLS. This integration empowers ASIP designers to customize RISC-V cores efficiently. Leveraging ASIP strengths, DELTA-V enables tailored SoC development, achieving over %60 cycle count reduction for efficient RISC-V processors with minimal effort.