FPGA Based Verification for the Difficulty of Delay Based Hardware Trojan Detection

Hardware Trojan insertion during the manufacturing phase is a crucial problem for chip designers. There are several approaches to detect the Trojan in circuits without destructing the chip structure. One of them is delay based hardware Trojan detection. However, this technique suffers deeply from the variations and it is a question whether the Trojans can be detected as the variations hide the effect of the Trojan. This paper, rather than simulation tools, performs experiments on actual FPGA chips to demonstrate and verify the contribution of both inter and intra die variations as well as the effect of hardware Trojan on delay. Lastly, the ability of delay based Trojan detection backed up by the ring oscillator is investigated with different sizes of the Trojan.