Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption

In this work, we elaborate on our endeavors to design, implement, fabricate, and post-silicon validate CoFHEE (Nabeel et al., 2023), a co-processor for low-level polynomial operations targeting fully homomorphic encryption execution. With a compact design area of
$12 {\mathrm{ mm}}^{2}$
, CoFHEE features ASIC implementations of fundamental polynomial operations, including polynomial addition and subtraction, Hadamard product, and number theoretic transform, which underlie most higher-level FHE primitives. CoFHEE is capable of natively supporting polynomial degrees of up to
$n = 2^{14}$
with a coefficient size of 128 bits, and has been fabricated and silicon-verified using 55-nm CMOS technology. To evaluate it, we conduct performance and power experiments on our chip, and compare it to state-of-the-art software implementations and other ASIC designs.