A D-Band Two-Way Differential Power Divider on 65-nm CMOS Process

A CMOS two-way differential power divider is proposed to reduce the insertion loss (IL) and size in the
$D$
-band. The power distribution is achieved using a low-loss differential power divider with a capacitive loading structure, without modifying the matching network of the unit devices. In addition, the degradation of the IL due to the parasitic inductance of groundings is made negligible by using the virtual ground of the differential structure. The impedance of the differential-mode transmission line (TL), which is half that of the single-ended line, is designed in the impedance range achievable in the bulk CMOS process, utilizing capacitive loading techniques. The 3-D electromagnetic (EM) simulation results of a two-way power divider show a low IL within 0.35 dB at 110–170 GHz. The proposed power divider achieves a measured minimum IL of 0.32 dB at 160 GHz with a core size of 0.0075 mm2.