Tungsten Interconnect Resistance Reduction Enabling Energy Efficient and High Performance Applications for 2nm Node and Beyond

We present a state-of-the-art Tungsten integration scheme for advanced technology nodes using integrated pre-clean, PVD W liner deposition, CVD W gapfill, and chemical mechanical planarization (CMP) process sequence. Electrical test results (resistance, reliability) combined with Materials-to-Systems Co-Optimization (MSCO
^TM
) simulations confirm significant power-performance-area (PPA) improvements, thereby enabling energy efficient, high-performance applications for 2nm technology node and beyond.