<1ppm Device to Chip Level Reliability Characterization for High-Density DDR5 DRAMs

An effective methodology of predicting the intrinsic failure rates <0.01ppm using hundreds of DRAM chips in one wafer was produced. This method was based on detecting the breakdown information on a much smaller unit per chip (Table I) through the full chip level stress that individual SWD (sub word-line driver) circuitry was monitored until failure was detected. Unlike previous methods that predict the statistical distribution with hundreds or thousands of test structures, >10
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samples at the transistor level was stressed at the same time, and its distribution was measured for the first time. Failure rates estimated to chip level with this data was consistent with those measured at the chip level, and is also applicable to devices which follows weibull clustering distribution. With this wafer main-chip characterization capable of applying high acceleration voltages, the 12nm DDR5 DRAM demonstrated the gate oxide reliability <1ppm at the chip level, and its early failures have been demonstrated through burn-in tests with chips of >10
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at the package level. In addition, all reliability including FEOL/MEOL/BEOL were also characterized using test structures and wafer main-chips.