Comprehensive Study of NBTI and Off-State Reliabilty in Sub-20 nm DRAM Technology: Trap Identification, Compact Aging Model, and Impact on Retention Degradation

With the introduction of High-κ/Metal Gate (HKMG) process, reliability has become a major challenge in the scaling of DRAM technology. Due to the different HK processes compared with logic technology, comprehensive studies of NBTI and Off-State Degradation (OSD) in DRAM peripheral devices are highly necessary. In this work, we distinguish various traps for their contributions to NBTI and OSD reliability. For the first time, we clarify the origin of NBTI traps in thick gate oxide HKMG DRAM peripheral transistors by determining their energy levels and relaxation energy distributions. Meanwhile, we systematically study OSD of DRAM for the first time in HKMG devices, presenting a different degradation result from SiON devices, and propose a new OSD mechanism that includes the impacts of both electron and hole traps. Based on the trap identification, we develop compact aging models from trap-based approach that can accurately predict degradation and facilitate decoupling analysis of aging components. Finally, we discuss the impact of Sub Wordline Driver (SWD) aging on retention degradation, indicating that an accurate aging model can assist designers to find a balance between speed and reliability. This work is helpful for design/technology co-optimization of DRAM peripheral circuits.