ESD Reliability in Advanced Nodes

Standard ESD protection structures continue to perform well in the most advanced logic technologies in use today. However, Power, Performance, and Area (PPA) considerations have increased pressure on using only the correct but not excessive amount of ESD protection. Increased use of within-package die-to-die connections has also introduced major challenges from an ESD design and testing perspective. This invited paper will describe the related challenges and efforts made on the device and product ESD qualification side to support these critical changes.