First Demonstration of Stacked 2T0C-DRAM Bit-Cell Constructed by Two-Layers of Vertical Channel-All-Around IGZO FETs Realizing 4F2 Area Cost

For the first time, we have realized the vertical-stacked 4F
²
2T0C DRAM cell constructed by two-layers of Channel-All-Around (CAA) IGZO FETs. The devices fabrication process is BEOL-compatible with the process temperature <250°C. The influences of monolithic stack on 1
^st
layer of devices have been investigated. By optimizing the IGZO-ALD deposition process, 2T0C bit-cell constructed by two CAA IGZO FETs is obtained, and a retention time of 75s has been experimentally verified, as well as good reliability. Our results demonstrate the feasibility of 4F
²
2T0C bit-cell based on stacked CAA IGZO FETs for high-density 3D DRAM application.