New Insights into the Interface Trap Generation during Hot Carrier Degradation: Impacts of Full-band Electronic Resonance, (100) vs (110), and nMOS vs pMOS

In this paper, the underlying physics of interface trap generation in CMOS devices are revealed, by using full-band distribution of H atom electronic resonance states in Si-H bond at Si/SiO
2
interface, instead of previously assumed single resonance level. The idea is verified and quantified by advanced time-dependent DFT (TDDFT) calculations. Based on this, the hot carrier degradation can be well modeled to surprisingly cover a broad range of technologies and stress conditions, due to the multiple peaks found in the full-band resonance states, and a TCAD simulation flow is proposed. The model is experimentally validated, from classic region (130nm Planar) to advanced region (16/14nm FinFET) and extendable to GAA, covering both (100) & (110) and n & p channels with various V
gs
/V
ds
bias conditions. This work provides a universal understanding and efficient simulation framework for the hot carrier reliability.