RF performance enhancement of 28nm FD-SOI transistors down to cryogenic temperature using back biasing

In this study, we investigate the back-gate bias impact on the electrical behavior of FD-SOI transistors from room temperature down to 4.2K. For the first time, we demonstrate how to improve the RF performances of transistors and circuits for cryoCMOS applications. DC and RF characterizations are presented providing an insight on the underlying physics. We then defined optimization guidelines and applied it to a Low Noise Amplifier (LNA) for operation at 4.2K