Improved Multi-bit Statistics of Novel Dual-gate IGZO 2T0C DRAM with In-cell VTH Compensation and ΔVSN/ΔVDATA Boosting Technique

For the first time, one novel dual-gate IGZO DRAM is proposed and demonstrated for multi-bit storage. Contrary to traditional 2T0C, the data is written into storage node through both write and read transistors, achieving novel in-cell V
TH
compensation without increasing bit-cell complexity. The optimized read transistor with positive V
TH
and high on-state current enables efficient V
TH
compensation with sub-10 ns writing speed. Meanwhile, owing to V
TH
modulation by additional gate of read transistor, great boost of differential voltage written into storage node (SN) is shown, with a record-high ratio (ΔV
SN
/ΔV
DATA
) of 1.46. By this design, 3-bit storage among 25 cells exhibits improved statistical distribution with one order reduction of standard deviation. This work paves the forward way for multi-bit IGZO 2T0C DRAM applications.